Graphics RISC Core
The EM8511 consists of at least three RISC cores: A primary ARM core for general purpose code execution (bootloader, os, menus, ide access, etc), a coprocessor core for memory management and bus IO, and a graphics core for video decoding, zooming, overlays, on-screen displays, etc.
Communication
The graphics core uses I2C (via PIO) and memory-mapped registers for communication with the main core.
PIO
The graphics core has 16 PIO pins, and thus uses only PIO0 (0x0050-0600) for PIO communications with the core.
DRAM Registers
The graphics DRAM is accessed via the Host Quasar Slave area (0x0050-1500). To write a full 4-byte double word, write to the HOST_SLAVE_WR_QUASAR_4BYTE port. To write fewer bytes, use on of the lesser ports. The write must be programmed via the memory mapped registers.
The DRAM is the main holding area for MPEG-video packets, audio packets, subpicture packets, and OSD packets. The graphics core "plays" streams of these packets to generate video, audio, subtitles/dvd menus (aka subpictures), and the OSD display.
//------------------------------------------------------
// HOST/QUASAR SLAVE REGISTERS 0x0050_1500
//------------------------------------------------------
#define JASPER_HOST_SLAVE_QUASAR_BASE 0x00501500
#define HOST_SLAVE_WR_QUASAR_BYTE 0x00000000
#define HOST_SLAVE_WR_QUASAR_1BYTE 0x00000000
#define HOST_SLAVE_WR_QUASAR_2BYTE 0x00000004
#define HOST_SLAVE_WR_QUASAR_3BYTE 0x00000008
#define HOST_SLAVE_WR_QUASAR_4BYTE 0x0000000C
#define HOST_SLAVE_RD_QUASAR_BYTE 0x00000000
#define HOST_SLAVE_RD_QUASAR_1BYTE 0x00000000
#define HOST_SLAVE_RD_QUASAR_2BYTE 0x00000004
#define HOST_SLAVE_RD_QUASAR_3BYTE 0x00000008
#define HOST_SLAVE_RD_QUASAR_4BYTE 0x0000000C
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The program memory (PM) and data memory (DM) can be accessed directly through the JASPER_QUASAR_* memory map area at 0x0060-0000. See the current microcode map for DM area register names.
//------------------------------------------------------
// QUASAR PM/DM AREA
//------------------------------------------------------
#define JASPER_QUASAR_BASE 0x00600000
#define QUASAR_MAP_AREA 0x00600000
#define QUASAR_PM_START 0x00600000
#define QUASAR_PM_SIZE 0x00002000
#define QUASAR_DM_START 0x00604000
#define QUASAR_DM_SIZE 0x00002000
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OSD
The Jasper EM85xx on-screen display is refreshed either (a) at the program's request or (b) automatically at the start of the VSync pulse (i.e. 25/30 times per second for PAL/NTSC respectively). Normally this is handled by the KHWL driver by simply sending the new frame to the graphics DRAM via the HOST_SLAVE_QUASAR ports, and notifying the card of an updated frame in the OSD "channel". The driver optionally performs RLE compression on the buffer during transfer to the video core.
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